Extreme ultraviolet (EUV) lithography is the printing process that transfers nanometer-scale circuit patterns onto silicon wafers. Its newest generation, High-NA, reached a commercial milestone in December 2025, when TechPowerUp reported that Intel installed ASML's TWINSCAN EXE:5200B scanner for its 14A node, with overlay accuracy of 0.7 nanometers documented by Tom's Hardware.
What does a lithography machine actually do?
A lithography scanner is a projection system. It shines light through a mask carrying one layer of a chip design, then shrinks and projects that pattern onto a light-sensitive layer on a silicon wafer. The wafer is shifted slightly and exposed again, building the chip layer by layer. Because modern processors stack dozens of patterned layers, every layer must land on top of the previous one with sub-nanometer precision. That alignment, called overlay, is the specification chipmakers watch most closely, because each misalignment reduces yield.
The light source is the second half of the story. EUV systems use extreme ultraviolet light with a wavelength of 13.5 nanometers, short enough to resolve features that older deep-ultraviolet tools cannot print in a single pass. Shorter wavelengths and larger numerical-aperture optics are the two levers that let each machine generation print finer features, which is how the industry keeps packing more transistors into the same slab of silicon. Everything else in the machine — the mirrors, the stages, the sensors — exists to keep that projected image still and sharp while the wafer moves underneath it at high speed.
Why is High-NA EUV different from the EUV before it?
High-NA raises the numerical aperture of the projection optics from 0.33 to 0.55, which sharpens resolution enough for the technology generations after today's leading-edge nodes. According to TechPowerUp's December 16, 2025 report, Intel's installation of the TWINSCAN EXE:5200B for its 14A node marks the first industry transition from Low-NA to High-NA in production development. The EXE:5200B is ASML's second version of its High-NA scanners, and Intel completed acceptance testing on the tool jointly with ASML to enhance wafer output.
The step is not just a brighter bulb. Tom's Hardware reports that one of the EXE:5200B's most consequential parameters is its overlay performance of 0.7 nanometers, achieved through advancements in stage control, sensor calibration, and environmental isolation. Tighter overlay matters because multi-pass and multi-exposure patterning — which the outlet reports will inevitably be used for sub-1-nanometer process technologies — only works when every repeated exposure lands exactly where the previous one did. An error that compounds across dozens of layers kills the die; an error held flat across every layer produces working chips.
How does a chip move from scanner to finished product?
The lithography step sits inside a longer loop, and each pass through the loop adds one layer of the final device. Based on the documented workflow around Intel's 14A development, the cycle looks like this:
- Designers prepare a mask carrying one layer of the circuit pattern.
- The scanner exposes that pattern onto the coated wafer with EUV light.
- Evaluation, etch, and deposition processes convert the exposed pattern into actual transistor or interconnect structures.
- Metrology tools measure overlay and critical dimensions against targets.
- The wafer returns to the scanner for the next layer, with corrections fed back from the measurement results.
The loop repeats dozens of times per wafer, and the scanner is only one station in it. That is why a lithography tool's productivity is measured in wafers per hour rather than in resolution alone: a fab buys the machine to run the loop as many times per day as physics allows. Acceptance testing of the kind Intel and ASML completed, as reported in December 2025, is the formal check that the tool meets those productivity and accuracy targets in the customer's own cleanroom rather than on the vendor's test floor.
What engineering problems did Intel's installation have to solve?
Tom's Hardware details several, and they read like a catalogue of everything that can move a pattern out of place. The scanner's stocker — the subsystem responsible for how wafers are stored, queued, and moved in and out of the scanner — was redesigned so wafers arrive at the exposure stage in a more predictable state, with tighter thermal control of wafers and carriers before and after exposure. Even tiny temperature variations cause wafer expansion or contraction, leading to overlay errors, which in turn increase defects and reduce yields.
Reducing thermal and mechanical variation also minimizes drift over long runs, enabling the scanner to maintain stable behavior and reducing the necessity for frequent recalibration, the report notes. Stability of that kind matters most for the multi-pass and multi-exposure patterning regimes ahead: a machine that drifts a fraction of a nanometer per hour cannot be trusted to run the same layer twice, let alone forty times. The environmental isolation that contributes to the 0.7-nanometer overlay figure is therefore not a comfort feature but the core of the machine's value proposition.
Who else gets to use this equipment?
For now, almost nobody. Intel is the industry's first mover on High-NA: TechPowerUp describes the EXE:5200B as the world's most advanced EUV machine and notes that Intel is producing its 14A node with the technology, the first such transition from Low-NA. Other leading foundries have publicly taken a slower path, continuing with Low-NA multi-patterning for their coming nodes, which keeps near-term tool costs lower at the price of more exposure passes per layer.
The result is an unusual split in manufacturing strategy at the leading edge. One camp buys fewer, more expensive scanners and prints each layer in fewer passes; the other keeps cheaper tools and stacks exposures. Which approach wins on cost per good wafer will shape who can afford the nodes after 14A-class technology — and the answer will not arrive until both approaches have run at volume, on real products, for several quarters.
Why should anyone outside the chip industry care?
Because lithography capability sets the ceiling for everything downstream. The resolution and overlay a scanner can hold determine how many transistors fit on a die, which determines how much compute, memory bandwidth, and efficiency the devices of the late 2020s can offer. Phone battery life, data-center power draw, and the cost of training AI models all trace back, several steps removed, to numbers like a 0.7-nanometer overlay spec.
The supply side matters too. High-NA EUV tools come from a single maker, ASML, in a supply chain stretching across optics, lasers, and precision mechatronics in multiple countries. A one-of-a-kind $350-million-class machine installed by one customer is a concentration of industrial capability that policy makers in the United States, Europe, and Asia watch closely. When the next technology transition arrives, who owns the tools and who can run them will be as decisive as who designed the chips.
